Doherty amplifiers are widely used in high frequency power amplifiers. A typical Doherty amplifier is shown in FIG. 1. It comprises a main power amplifier (PA) and a peak PA. The power amplifiers are implemented using different technologies as LDMOS, HEMT, etc. An input signal applied at an input terminal of the amplifier is divided into two components. A first component is applied to the main PA and a second component is applied to a phase shifter Z01 which is adapted to phase shift the input signal with 90°. The phase shifted second component is inputted to the peak PA. The main PA delivers an amplified version of the first component which is applied to an input of second phase shifter Z01 which is substantial identical to the first phase shifter. A phase shifted version of the amplified version of the first component is combined with a signal delivered by the peak PA. The combined signal is then applied to the input of a third phase shifter Z02, which is phase shifting the combined signal with 90°. The phase shifted signal is then applied to an output terminal. Particularly, the peak PA and the main PA are each transistors having a gate input.
Throughout this description we shall keep this terminology even if the amplifiers are implemented using more than one transistor. In this case a gate input refers to the gate of a transistor included in the PA and which receives a control signal. At the same time, a drain input refers to a drain terminal of a transistor included in the PA and which is used for supplying the transistor. It is understood that in specific cases the gate input could coincide with the input of the PA.
The Doherty amplifier may be implemented using two amplifying stages either for the peak PA or for the main PA or for both. An example of such a two stage amplifier is shown in FIG. 2. It comprises a first driver transistor T1 coupled to a power transistor T2 via an inter-stage matching circuit 20. The first driver transistor T1 receives an input signal via an input matching circuit 10 which is used for adapting the input impedance of the driver transistor with an impedance of a generator which generates the input signal. An output signal generated by the power transistor T2 is outputted to a receiver (not shown in the figure) via an output matching circuit 30 which adapts an output impedance of the power transistor T2 with an input impedance of the receiver.